1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method to be formed by an SAS technique, and more particularly to a nonvolatile semiconductor memory device and its manufacturing method in which one side edge of word lines (or control gate electrodes) are used as a part of a mask, grooves or trenches are formed in a gate insulating film and a field oxide film, impurity is introduced into a semiconductor substrate exposed to a bottom of the grooves, thereby forming source regions of a memory cell transistors and a common source wiring region for connecting the source regions.
2. Description of the Related Art
Conventionally, in a nonvolatile semiconductor memory device such as an EPROM memory cell transistor, one side edge of word lines (or control gate electrodes) are used as a part of a mask, grooves are formed in a gate insulating film and a field oxide film, and impurity is ion-implanted in a semiconductor substrate exposed in the grooves, thereby forming source regions of the memory cell transistors and a common source wiring region for electrically connecting the source regions in a self-aligning manner. This method is called as a self aligned source (SAS), and is described in, for example, U.S. Pat. No. 5,019,527 and U.S. Pat. No. 4,500,899.
The EPROM memory cell transistor is formed by the SAS technique, the source regions and the common source wiring region (the combination of the source regions and the common source wiring region is referred to herein as a common source region) can be formed in control gate electrodes in a self-aligning manner. As a result, allowance for masking can be generated, high integration can be easily made, and manufacture yield can be improved.
In order to improve the electrical characteristic of the transistor, it is known that the junction depth of an impurity diffusion layer serving as a source region is must be shallowly formed. However, according to the conventional SAS technique, one impurity diffusion layer is used as source regions and a common source wiring region. In other words, the source regions and the common source wiring region are formed by one impurity diffusion process. Due to this, if the source regions are shallowly formed, the common source wiring region is also shallowly formed. As a result, since the wiring resistance of the common source wiring region is increased and the voltage largely drops at this portion, it is difficult to make an operation speed higher. This becomes a remarkable problem when the width of the wiring region is made narrow and high integration advances.